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Germanium Quantum Technology

01 /What can CMOS technology do for quantum computing? 02 /Semiconductor devices and scaling with industrial approach 03 /Semiconductor foundry facilities: the good and the bad for qubits 04 /IMEC's latest qubit developments 05 /Summary and outlook 06 /Semiconductors for spin qubits 07 /Germanium quantum wells on silicon 08 /Germanium quantum wells on silicon-germanium 09 /Growth methods 10 /Characterization techniques 11 /Electrical characterization of germanium quantum wells 12 /Fabrication of H-FET 13 /Semiconductor qubits: vision and challenges 14 /Quantum materials 15 /Quantum dot qubits and their operation 16 /Types of quantum dot qubits 17 /Qubit Readout 18 /Qubit Control 19 /Qubit Coherence and Fidelity 20 /Multi-qubit control and quantum algorithms 21 /Quantum links and scaling 22 /Physics of holes 23 /Hole spin qubits 24 /Introduction to electronics for quantum computing 25 /Room temperature electronics 26 /Cryogenic qubit chip carriers 27 /Contribution to IGNITE 28 /Quantum Control Stack for Spin Qubits 29 /Auto-tuning a quantum computer 30 /Tuning and operation of arrays 31 /Finding operation points example 32 /What is auto-tuning? 33 /Neural network tuning 34 /Navigating charge stability diagrams 35 /Experimental implementation 36 /Towards universal quantum algorithms 37 /Classical error correction 38 /Quantum error correction 39 /Progress and challenges 40 /Introduction to quantum algorithms 41 /The first algorithms 42 /Quantum annealing 43 /Quantum Machine Learning

Semiconductor devices and scaling with industrial approach

In this video, you will have a brief overview of the scaling of the CMOS industry. The evolution of the transistor structure, the wafer size, the scaling challenges, and device architecture will be discussed.

Prerequisite knowledge

  • CMOS technology 
  • Semiconductors 

Main takeaways

  • For scaling requirements, the real transistor structures are very different to textbook style structures.  
  • The scaling of transistors for different technology nodes gives better performance, lower power, smaller area, and lower cost. 
  • There are different challenges along the scaling of semiconductor devices.  

Further thinking

True or False: 300mm wafers are used in the state-of-the art semiconductor fabrication flow.

Solution

Further reading

The Blog by Prof. Douglas Natelson at Rice University on industrial fabrication for quantum computing

nanoscale views: Bringing modern industrial nanofab to quantum computing

For research on qubits integrated with advance CMOS technology, you can check these papers:

https://arxiv.org/abs/1605.07599
https://arxiv.org/abs/2102.03929
https://arxiv.org/abs/2101.12650
https://arxiv.org/abs/2202.10303